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Publications

Journal Papers 

  1. T. Musah, J. E. Jaussi, G. Balamurugan, S. Hyvonen, T.-C. Hsueh, G. Keskin, S. Shekhar, J. Kennedy, S. Sen, R. Inti, M. Mansuri, M. Leddige, B. Horine, C. Roberts, R. Mooney, B. Casper, "A 4-32Gb/s Bidirectional Link with 3-tap FFE/6-tap DFE and Collaborative CDR in 22nm CMOS," IEEE J. Solid-State Circuits (JSSC), vol. 49, no. 12, pp. 3079-3090, Dec. 2014.
  2. T. Musah and U. Moon, "Correlated level shifting integrator with reduced sensitivity to amplifier gain," Electron. Lett. (EL), vol. 47, no. 2, pp. 91-92, Jan. 29, 2011.
  3. Y. Hu, N, Maghari, T. Musah, and U. Moon, "Time-interleaved noise-shaping integrating quantisers," Electron. Lett. (EL), vol. 46, no. 11, pp. 757-758, May 27, 2010.
  4. O. Rajaee, T. Musah, N. Maghari, S. Takeuchi, M. Aniya, K. Hamashita, and U. Moon, "Design of a 79dB 80MHz 8X-OSR hybrid delta-sigma/pipeline ADC," IEEE J. Solid-State Circuits (JSSC), vol. 45, no. 4, pp. 719-730, Apr. 2010.
  5. T. Musah and U. Moon, "Correlated level shifting technique with cross-coupled gain-enhancement capacitors," Electron. Lett. (EL), vol. 45, no. 13, pp. 672-674, Jun. 18, 2009.
  6. T. Musah, B.R. Gregoire, E. Naviasky, and U. Moon, "Parallel correlated double sampling technique for pipelined analogue-to-digital converters," Electron. Lett. (EL), vol. 43, no. 23, Nov. 8, 2007.

Conference Papers

  1. J. E. Jaussi, G. Balamurugan, S. Hyvonen, T.-C. Hsueh, T. Musah, G. Keskin, S. Shekhar, J. Kennedy, S. Sen, R. Inti, M. Mansuri, M. Leddige, B. Horine, C. Roberts, R. Mooney, B. Casper, "A 205mW 32Gb/s 3-Tap FFE/6-Tap DFE Bi-directional Serial Link in 22nm CMOS," IEEE Int. Solid-State Circuits Conf. (ISSCC), pp. 440-441, Feb. 2014.
  2. T.-C. Hsueh, G. Balamurugan, J. Jaussi, S. Hyvonen, J. Kennedy, G. Keskin, T. Musah, S. Shekhar, R. Inti, S. Sen, M. Mansuri, C. Roberts, B. Casper, "A 25.6Gb/s Differential and DDR4/GDDR5 Dual-Mode Transmitter with Digital Clock Calibration in 22nm CMOS," IEEE Int. Solid-State Circuits Conf. (ISSCC), pp. 444-445, Feb. 2014.
  3. B. Hershberg, T. Musah, S. Weaver, and U. Moon, "The effect of correlated level shifting on noise performance in switched capacitor circuits," IEEE Int. Symp. Circuits Syst. (ISCAS), pp. 942-945, May 2012.
  4. B.R. Gregoire, T. Musah, N. Maghari, S. Weaver, and U. Moon, "A 30% beyond Vdd signal swing 9-ENOB pipelined ADC using a 1.2V 30dB loop-gain opamp," IEEE Asian Solid-State Circuits Conf. (ASSCC), pp. 345-348, Nov. 2011.
  5. O. Rajaee, Y. Hu, M. Gande, T. Musah, and U. Moon, "An interstage correlated double sampling technique for switched-capacitor gain stages," IEEE Int. Symp. Circuits Syst. (ISCAS), pp. 1252-1255, May 2010.
  6. T. Musah and U. Moon, "Pseudo-differential zero-crossing-based circuits with differential error suppression," IEEE Int. Symp. Circuits Syst. (ISCAS), pp. 1731-1734, May 2010.
  7. T. Musah, S. Kwon, H. Lakdawala, K. Soumyanath, and U. Moon, "A 630uW zero-crossing-based delta-sigma ADC using switched-resistor current sources in 45nm CMOS," IEEE Custom Int. Circuits Conf. (CICC), pp. 1-4, Sep. 2009.
  8. O. Rajaee, T. Musah, S. Takeuchi, M. Aniya, K. Hamashita, P. Hanumolu, and U. Moon, "A 79dB 80MHz 8X-OSR hybrid delta-sigma/pipeline ADC," IEEE Symp. VLSI Circuits (VLSI), pp. 74-75, Jun. 2009.
  9. S. Chatterjee, T. Musah, Y. Tsividis, and P. Kinget, "Weak inversion MOS varactors for 0.5 V analog integrated filters," IEEE Symp. VLSI Circuits (VLSI), Jun. 2005, pp. 272-275.

Graduate Thesis

  1. Tawfiq Musah, "Low power design techniques for analog-to-digital converters in submicron CMOS," Ph.D. Dissertation, Oregon State University, 2010.

Patents

  1. J. P. Kulkarni, A. Ravi, D. Somasekhar, G. Balamurugan, S. Shekhar, T. Musah, T.-C. Hsueh, “Digitally trimmable integrated resistors including resistive memory elements,” US Patent Number: 10347309, Jul. 2019
  2. T. Musah, H. Venktramam, B. Casper, "Low power high speed receiver with reduced decision feedback equalizer samplers," US Patent Number: 10341145, Jul. 2019.
  3. T. Musah, G. Keskin, G. Balamurugan, J. E. Jaussi, and B. Casper, “Wireline receiver circuitry having collaborative timing recovery,” US Patent Number: 9794089, Oct. 2017.
  4. J. P. Kulkarni, A. Ravi, D. Somasekhar, G. Balamurugan, S. Shekhar, T. Musah, T.-C. Hsueh, “Digitally trimmable integrated resistors including resistive memory elements,” US Patent Number: 9589615, Mar. 2017.
  5. H. Venkatram, S. Hyvonen, T. Musah, and B. Casper, “High speed receiver with one-hot decision feedback equalizer,” US Patent Number: 9537682, Jan. 2017.
  6. T. Musah, G. Keskin, G. Balamurugan, J. E. Jaussi, and B. Casper, “Wireline receiver circuitry having collaborative timing recovery,” US Patent Number: 9374250, Jun. 2016.