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High efficiency ADCs for digital receivers

Digital receiver equalizers have become the go to equalization architectures for high loss channels. One of the reasons for this is that they obviate the trade-off between number of DFE taps and data rate. Also, they enable multi-standard use of the hardware due to their high programmability. Moreover, the highly digital designs they enable can be easily ported from one technology to another. However, current ADC-based receiver designs still lag their mixed-mode counterparts in power and area efficiency. A major cause of this power efficiency gap is the complexity of the analog-to-digital converter (ADC) in the front-end. In this research thrust, we combine our extensive prior work on ADCs [see MusahCICC09, RajaeeJSSC10] with serial I/O system expertise to explore new digital receiver topologies that yield higher area and power efficiencies.