Robust CDRs for PAM4+ signaling
Clock and data recovery (CDR) schemes in serial I/Os rely on phase detectors (PD) that come in several flavors, but they can all be grouped under oversampled and baud rate phase detectors. Both of these PD schemes add to receiver complexity because of the need for additional comparators, and extra clock phases in the case of oversampled PDs. This added complexity only increases in the case of multi-level signaling, like PAM 4 or higher order PAM. Additionally, there is increased uncertainty in the lock point due to multiple zero-crossings in the PAM N eyes (for N>2). While oversampled PDs offer the ability to use transition filtering to mitigate the lock point uncertainties, they may not be feasible in high data rate applications. For this research thrust, we will be investigating CDR techniques and timing functions that enable robust timing recovery for applications utilization advanced modulation while ensuring minimal receiver overhead.